The present invention relates to semiconductor devices, and more specifically to a method of making a structure having a conductive via to a semiconductor device region.
In fabricating integrated circuits in conventional bulk semiconductor wafers, wells of either P-type or N-type conductivity are implanted in a substrate of the opposite conductivity. However, in complementary metal oxide semiconductor (CMOS) technology, both p-type and n-type wells are utilized. Source/drain regions are formed by implanting diffusion regions of the opposite n-type or p-type conductivity as the wells to form metal-oxide-semiconductor field effect transistors (MOSFETs). Recent theoretical and empirical studies have also demonstrated that carrier mobility in a transistor can be increased when a stress of sufficient magnitude is applied to the conduction channel of a transistor to create a strain therein. An increase in the performance of an n-type field effect transistor (NFET) can be achieved by applying a tensile longitudinal stress to the conduction channel of the NFET. An increase in the performance of a p-type field effect transistor (PFET) can be achieved by applying a compressive longitudinal stress to the conduction channel of the PFET.
A stress-imparting film, also referred to herein as a “stressed” film, can be deposited to cover a semiconductor device region to impart a stress thereto for enhancing the conductivity of a transistor, for example, an NFET or a PFET device. Silicon nitride is one material, among others, which can be deposited in such way that the resulting material layer imparts either a tensile stress or a compressive stress to a layer of a second material with which it is in contact. To improve the conductivity of both an NFET and a PFET, a tensile stress-imparting nitride can be formed to cover an NFET device region and a compressive stress-imparting nitride can be formed to cover a PFET device region.
Silicon nitride and other materials are sometimes used to provide a protective barrier to protect against the diffusion of materials which can degrade the performance of semiconductor devices such as FETs. A barrier is especially needed because one or more metals, e.g., copper, used in wiring at levels above the device can diffuse through an intervening dielectric layer to contaminate devices formed at the semiconductor level. However, the presence of a barrier layer can make the fabrication of a conductive via contacting the device more difficult, particularly when an additional layer, e.g., a stress-imparting nitride, is already present as a layer blanketing the semiconductor device region. This concern is best explained with reference to FIG. 1.
FIG. 1 is a cross-sectional view illustrating use of such barrier layer 108. As shown in FIG. 1, a stressed film 105, such as a silicon nitride layer having an internal stress, is disposed as a layer covering a device provided in a semiconductor device region 100. The stressed film 105 also covers features, such as polysilicon conductors (PCs) 150, which are disposed over the semiconductor device region. A barrier layer 108 is deposited to overlie the stressed film. This structure makes it difficult to etch the contact holes that are necessary to form conductive vias to contact the semiconductor device region 100. One contact hole is to be etched along the dotted line 130 to provide a conductive via to the semiconductor device region 100 at a location disposed between respective features such as the PCs 150. Another contact hole is to be etched simultaneously at another location 112, so as to provide a conductive via contacting the PC 150. However, it is difficult to adequately perform and control the simultaneous etching of both contact holes because the thickness of the material making up the stressed film and the barrier layer at the two locations is different. Namely, the combined thickness 120 of the two layers 108, 105 is much greater at location 130 where the contact via is to extend to the semiconductor device region 100 than the thickness 110 of the two layers at location 112 where the contact via to the PC 150 is to be formed. Consequently, problems can result from such etching, such as excessive overetching into the PC 150 at the location 112 where the stressed film and the barrier layer are thinner. Alternatively, the contact hole may not be adequately etched through the stressed film and the barrier layer at location 130, causing the final contact via to show excessive resistance.
Consequently, a need exists for a structure and method of fabricating a semiconductor device in which a protective barrier layer is provided, while permitting contact vias to be etched with less difficulty.